news

Jan 24, 2025	Happy to announce that I passed my viva with minor corrections today! Huge thank you to my examiners Ally Donaldson (Imperial) and Tom Melham (Oxford). Was a great discussion and followed by celebrations with many friends old and new.
Nov 30, 2024	Excited to have my first papers accepted at FPGA and DVCON. Raf will be presenting our work on fixing datapath bugs at DVCON, whilst second-year undergraduate Olly Cassidy will be presenting work that I helped shape into the final paper with Marta Andronic.
Jun 10, 2024	At ARITH this year both Theo Drane and I presented papers. I presented the final work of my PhD Combining Power and Arithmetic Optimization via Datapath Rewriting, whilst Theo presented our second paper On the Systematic Creation of Faithfully Rounded Commutative Truncated Booth Multipliers! This was my first in-person ARITH so was great to meet many people for the first time, I particularly enjoyed Andrew Fitzgibbon’s keynote on ML number formats .
Apr 27, 2024	Raf presented our paper SEER: Super-Optimization Explorer for High-Level Synthesis using E-graph Rewriting at ASPLOS 2024! Had a great time working with Jianyi Cheng on this paper, where we combined e-graph rewriting and MLIR.
Oct 27, 2023	Went to Iowa to present our paper Datapath Verification via Word-Level E-Graph Rewriting at FMCAD 2023! A great conference with lots of interest in the work, many thanks to the organizers.
Oct 1, 2023	Our paper Multiplier Optimization via E-Graph Rewriting will be presented at ASILOMAR 2023! Looking forward to seeing everyone in a few weeks!
Oct 1, 2023	Our paper Datapath Verification via Word-Level E-Graph Rewriting will be presented at FMCAD 2023! Looking forward to seeing everyone in a few weeks!
Apr 25, 2023	Our paper Combining E-Graphs with Abstract Interpretation was accepted for publication at the SOAP Workshop co-located with PLDI 203!
Feb 20, 2023	Our paper Automating Constraint-Aware Datapath Optimization using E-Graphs was accepted for publication at DAC!